This application claims priority to Japanese Patent Application Number 2001-057499 filed Mar. 1, 2001, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor memory device such as, for example, an electrically rewritable nonvolatile memory. In particular, the present invention relates to a reference voltage generation circuit used for a plurality of sense amplifiers for simultaneously reading information from a plurality of memory cells using a reference voltage obtained from a reference cell, a memory reading circuit including such a reference voltage generation circuit, and an electronic information device, such as, for example, a cellular phone or a computer using such a memory reading circuit.
2. Description of the Related Art
Conventionally, semiconductor memory devices such as, for example, EEPROMs (Electrically Erasable and Programmable Read Only Memories) and flash EEPROMs (hereinafter, referred to as the xe2x80x9cflash memoriesxe2x80x9d) are known as electrically rewritable nonvolatile memories. These semiconductor memory devices each include a sense amplifier circuit (sense amplifier) and circuits related thereto as a memory reading circuit for reading information memory cell transistors (hereinafter, referred to as xe2x80x9cmemory cellsxe2x80x9d).
An exemplary structure of a sense amplifier circuit and circuits related thereto is now described. In this example, a memory cell, from which the sense amplifier and the like read information, includes a stacking gate electrode, which is formed of polycrystalline silicon and has a two-layer structure of a control gate electrode and a floating gate electrode.
According to one operating principle of a memory cell having a stacking gate structure, information is stored based on whether the floating gate electrode is in a state of containing electrons or in a state of not containing electrons.
Herein, an operation for placing the floating gate electrode into a state of containing electrons will be referred to as a xe2x80x9cwriting operationxe2x80x9d, and an operation for placing the floating gate electrode into a state of not containing electrons will be referred to as an xe2x80x9cerasing operationxe2x80x9d. The writing operation and the erasing operation will not be described in detail.
A memory cell in which the floating gate electrode is in the state of containing electrons (obtained by the writing operation) will be referred to as a xe2x80x9cprogram cellxe2x80x9d. A memory cell in which the floating gate electrode is in the state of not containing electrons (obtained by the erasing operation) will be referred to as an xe2x80x9cerase cellxe2x80x9d. When a voltage is applied to the control gate electrode and a bias voltage is applied to a source electrode and a drain electrode of each of the program cell and the erase cell, the amount of current flowing in the program cell is smaller than that in the erase cell. (The state in which the above-mentioned voltages are applied to the control gate electrode, the source electrode and the drain electrode will be referred to as a xe2x80x9cmemory cell reading conditionxe2x80x9d). The reason that the amount of current flowing in the program cell is smaller is because in accordance with whether the floating gate electrode contains electrons or not, the electric field intensity, applied to the channel region of the memory cell when a voltage is applied to the control gate electrode, changes, thus the amount of current flowing in the memory cell also changes. The electric field intensity, obtained when a voltage is applied to the control gate electrode, changes in accordance with the number of electrons existing in the floating gate electrode. In accordance with the electric field intensity, the amount of current changes as described above. Here, whether the floating gate electrode contains electrons or not indicates whether the number of electrons in the floating gate electrode is relatively large or small.
By the above-described principle, data value xe2x80x9c0xe2x80x9d is stored in a memory cell when the amount of current is small, and data value xe2x80x9c1xe2x80x9d is stored in a memory cell when the amount of current is large.
The sense amplifier circuit determines whether the amount of current flowing in each memory cell under the memory cell reading condition is small or large, and outputs data value xe2x80x9c0xe2x80x9d or data value xe2x80x9c1xe2x80x9d based on the determination result. The determination on whether the amount of current is small or large can be made with respect to the amount of a reference current. In this case, a transistor having a structure similar to that of the memory cells (hereinafter, referred to as a xe2x80x9creference cellxe2x80x9d) can be used in order to produce the reference current. Such a transistor is produced so as to have the same influences of the temperature characteristics and voltage characteristics for reading memory cells as those of the memory cells.
The current amount of the reference cell can be an intermediate value between the current amount of the program cell and the current amount of the erase cell. The number of electrons in the floating gate electrode of the reference cell can be adjusted to be between the number of electrons in the floating gate electrode of the program cell and that of the erase cell.
FIG. 10 is a circuit configuration of a sense amplifier circuit 100 in a conventional flash memory. As shown in FIG. 10, the sense amplifier circuit 100 includes a memory cell section 101 including a selection circuit; a feedback-type current detection circuit 102, which is connected to a drain electrode of a memory cell 101b for reading (reading memory cell 101b) through a selection transistor 101a of the selection circuit; a reference cell section 103 acting as a reference current generation circuit and having a structure similar to that of the reading memory cell 101b, the reference cell section 103 also including a selection circuit; a feedback-type current detection circuit 104 having a structure similar to that of the reading memory cell 101b and connected to a drain electrode of a reference cell 103b through a selection transistor 103a of the selection circuit; and a comparator circuit 105 for comparing a voltage output from the reading memory cell 101b and a voltage output from the reference cell 103b. 
The current detection circuits 102 and 104 each use a load circuit for performing current-voltage conversion in order to obtain a voltage, which is to be output to the comparator circuit 105. Transistor loads 102a and 104a shown in FIG. 11 and resistance loads 102b and 104b shown in FIG. 12 are examples of such a load circuit.
In order to perform a reading operation from the reading memory cell 101b, the sense amplifier circuit 100 shown in FIG. 10 can include a charging circuit 106 for providing the drain electrode of the reading memory cell 101b with a bias voltage of the memory cell reading condition, and can also include a charging circuit 107 for providing the drain electrode of the reference cell 103b with a bias voltage of the memory cell reading condition.
With reference to FIG. 10, a reading operation performed on the conventional sense amplifier circuit 100 will be described.
As shown in FIG. 10, a gate voltage to be applied for performing the reading operation (hereinafter, referred to as a xe2x80x9creading gate voltagexe2x80x9d) is applied to the control gate electrode of the reading memory cell 101b selected by the selection transistor 101a. Simultaneously, a drain voltage to be applied for performing the reading operation (hereinafter, referred to as a xe2x80x9creading drain voltagexe2x80x9d) is applied to the drain electrode of the selected reading memory cell 101b through the selection transistor 101a by the charging circuit 106, transistor load 102a (FIG. 11) and the resistance load 102b (FIG. 12).
The charging circuits 106 and 107 operates until the drain electrode of the memory cell 101b and the drain electrode of the reference cell 103b obtain the drain voltage of the memory cell reading condition. After the drain voltage is reached, the charging circuits 106 and 107 stop operating. A source electrode of the selected reading memory cell 101b is grounded through a transistor or the like, and thus a current flows between the drain electrode and the source electrode of the selected reading memory cell 101b (hereinafter, this current will be referred to as a xe2x80x9creading currentxe2x80x9d).
The reading current is converted into a voltage by the load of the current detection circuit 102, and the voltage is input to one of two input ends of the comparator circuit 105 (Hereinafter, this voltage will be referred to as a xe2x80x9creading voltagexe2x80x9d).
Substantially the same operation is performed for the reference cell 103b. As a result, a reference current flows between the drain electrode and the source electrode of the reference cell 103b. The reference current is converted into a voltage by the load of the current detection circuit 104, and the voltage is input to the other input end of the comparator circuit 105 (hereinafter, the voltage obtained from the reference current will be referred to as a xe2x80x9creference voltagexe2x80x9d).
The reading current of a selected reading memory cell 101b containing electrons in the floating gate electrode, i.e., the program cell, is smaller than the reference current. The reading current is converted into a voltage by the load of the feedback-type current detection circuit 102 as described above. The obtained reading voltage is higher than the reference voltage obtained from the reference cell 103b. The reading voltage and the reference voltage respectively pass through the load of the feedback-type current detection circuits 102 and 104. Therefore, the difference between the reading voltage and the reference voltage is amplified as compared to the case where there is no load provided in the feedback-type current detection circuit 102 or 104.
The reading voltage and the reference voltage are compared by the comparator circuit 105, and the comparison result is output as a memory information reading result in the form of an xe2x80x9cLxe2x80x9d (low) level potential or an xe2x80x9cHxe2x80x9d (high) level potential.
The reading voltage of a selected reading memory cell 101b not containing electrons in the floating gate electrode, i.e., the erase cell, is lower than the reference voltage. In this case, the comparator circuit 105 outputs a memory information reading result which is inverted from that of the program cell.
Ideally, one sense amplifier circuit 100 shown in FIG. 10 is provided for reading information from each memory cell 101b (1 bit). In order to improve the functionality of the flash memory, however, it is sometimes required that one sense amplifier circuit 100, as shown in FIG. 10, should be provided for reading information from a plurality of cells (a plurality of bits). In this case, as shown in FIG. 13, the reference cell 103b and the current detection circuit 104 (using the load) can be commonly used for reading information from a plurality of memory cells 101b. In such a structure, the reference voltage output from the current detection circuit 104 (provided for the reference current) is sent to the comparator circuits 105 respectively provided for the plurality of memory cells 101b. 
FIG. 14 shows a configuration of a differential amplifier as one specific example of the comparator circuit 105. The reading voltage and the reference voltage are respectively input to the gate electrode of a transistor 105A (gate voltage) and the gate electrode of a transistor 105B (gate voltage) provided in the comparator circuit 105. The differential amplifier is operated in this state. Then, a current corresponding to the gate voltage of the transistor 105A flows between the source and the drain of the transistor 105A, and a current corresponding to the gate voltage of the transistor 105B flows between the source and the drain of the transistor 105B.
The current flowing between the drain electrode and the source electrode influences the gate voltage because of a generally known coupling effect of a gate oxide layer acting as a capacitor. The gate oxide layer is provided between the gate electrode and the source electrode/drain electrode/channel region of the transistors 105A and 105B.
In the case where the reference voltage is input to only one differential amplifier, the influence caused by the coupling effect is negligible for the reading operation.
By contrast, in the case where the reference voltage is commonly input to a plurality of differential amplifiers, the influence caused by the coupling effect on the reference voltage increases as the number of differential amplifiers increases. As a result, the difference between the influence caused by the coupling effect on the reference voltage and the influence caused by the coupling effect on the reading voltage excessively increases, and may undesirably influence the reading operation.
When the differential amplifiers are not intermittently operated, the influence caused by the coupling effect disappears in time and the reading operation is returned to normal even though data is incorrectly read while the reading operation is influenced by the coupling effect.
However, the influence caused by the coupling effect still has the following problems.
When data is incorrectly read under the influence caused by the coupling effect, the reading speed of the memory cell is slower as compared to the case where there is no influence caused by the coupling effect.
In order to reduce the operating current, the differential amplifier is sometimes operated as follows. The differential amplifier is operated during a certain time period to perform a reading operation from a selected memory cell, and after data from the differential amplifier is sent to and stored in a latch circuit or the like, the differential amplifier stops operating and outputs the read data from the reading circuit. In such a manner of operation, data needs to be read correctly in the above-mentioned xe2x80x9ccertain time periodxe2x80x9d.
When the influence caused by the coupling effect is excessive, the xe2x80x9ccertain time periodxe2x80x9d becomes too long to realize a high speed reading operation. In order to prevent the coupling effect from influencing the reading operation, the reference voltage and the reading voltage need to have a potential difference therebetween which does not results in the influence caused by the coupling effect. However, it is becoming more and more difficult to keep the difference between the reading current and the reference current sufficiently large, due to reduction in the memory cell current necessitated by recent demand for reducing the size of memories.
The difference between the reading current and the reference current can be kept sufficiently large by increasing the voltage difference between the source electrode and the drain electrode of the memory cell itself so that a larger amount of current flows in the memory cell. However, in actuality, the drain voltage cannot be very high since an excessively high drain voltage may destroy the state of containing electrons of the floating gate electrode which is formed by the writing operation.
For these reasons, the difference between the reading voltage and the reference voltage is not very large, and thus it is very difficult to acquire the voltage difference necessary to prevent the influence caused by the coupling effect.
Even in a sense amplifier circuit disclosed in Japanese Laid-Open Publication No. 11-306782 including a different type of comparator circuit, the influence caused by the coupling effect cannot be ignored.
In order to solve the above-described problems, the xe2x80x9cSemiconductor Memory Devicexe2x80x9d disclosed in Japanese Laid-Open Publication No. 2000-30475 is a proposed system for generating a reference current and a reference voltage for a plurality of sense amplifier circuits and simultaneously operating the plurality of sense amplifier circuits without increasing the chip area. Such a system is shown in FIG. 15.
The system disclosed in Japanese Laid-Open Publication No. 2000-30475 includes a reference cell block 110. The reference cell block 110 includes a circuit 110A corresponding to the reference cell 103b (FIG. 10) and a current mirror circuit 110B.
As shown in FIG. 16, a current source having characteristics similar to those of the reference cell block 110 is generated by the current mirror circuit 110B in at least one reference cell block 110 and is supplied to a plurality of sense amplifier circuits 111 as a reference current.
Such a structure avoids the above-described influence caused by the coupling effect. However, when a plurality of reference currents, for example, 16 are generated by one reference cell block 111, 16 gate capacitances can be connected to a node N in FIG. 16. When the number of gate capacitances is excessively large, the current characteristics are delayed between the time when the current is generated by the reference cell block 110 and the time when the current is supplied to the sense amplifiers 111.
When the number of gate capacitances connected to the node N is excessively large, time is required for charging the node N to a desired potential. During a time period in which the node N has not been charged to the desired potential, the current amount of each of the plurality of reference currents is different from the current amount desired to be finally obtained. When the characteristics of the reference current are delayed between the time of generation and the time of supply, it is necessary to wait for the delay to be eliminated. Thus, a high speed reading operation of information in the memory cells is prevented.
The reference voltage generation circuit disclosed in Japanese Laid-Open Publication No. 2000-30475 does not have a function of amplification. Therefore, when the amount of current in a memory cell is reduced, the sensitivity of the sense amplifier circuit is deteriorated, which also prevents a high speed reading operation of information in the memory cells.
A reference voltage generation circuit includes at least one reference cell having a source electrode and a drain electrode; a plurality of first sense circuits connected to the reference cell and including an N-channel transistor, a P-channel transistor, a plurality of input ends and a plurality of output ends; and a plurality of second sense circuits each for receiving an output from a corresponding one of the plurality of first sense circuits, the plurality of second sense circuits each having a load circuit, an N-channel transistor, a plurality of input ends and a plurality of output ends.
In one embodiment of the invention, the plurality of first sense circuits each generate a first duplicate voltage based on a voltage from the reference cell, and the plurality of second sense circuits each generate a second duplicate voltage based on the first duplicate voltage.
In one embodiment of the invention, the memory reading circuit for a semiconductor memory device includes the above-described reference voltage generation circuit; a third sense circuit connected to a selected memory cell and having an N-channel transistor, a P-channel transistor, a plurality of input ends and a plurality of output ends; and a fourth sense circuit for receiving an output from the third sense circuit, the fourth sense circuit having a load circuit, an N-channel transistor, a plurality of input ends and a plurality of output ends. The information is read using an output from each of the plurality of second sense circuits and an output from the fourth sense circuit.
In one embodiment of the invention, in the memory reading circuit for reading information from the selected memory cell by supplying a reference voltage to one of two input ends of a sense amplifier and supplying a voltage from the selected memory cell to the other of the two input ends, an output from each of the plurality of second sense circuits and an output from the fourth sense circuit are input to the sense amplifier.
In one embodiment of the invention, the load circuit of each of the plurality of second sense circuits of the reference voltage generation circuit is a P-channel transistor, and the load circuit of the fourth sense circuit is a P-channel transistor. A gate electrode and a drain electrode of one of the plurality of second sense circuits are connected to a gate electrode of the P-channel transistor of the fourth sense circuit, so that a load characteristic of the fourth sense circuit is equal to a load characteristic of the one of the plurality of second sense circuits.
In one embodiment of the invention, the reference voltage generation circuit shortcircuits an output from the fourth sense circuit and an output from the one of the plurality of second sense circuits through a transistor, and the output from the fourth sense circuit and the output from the one of the plurality of second sense circuits are transferred to a respective prescribed potential from the same level after being released from the shortcircuiting.
In one embodiment of the invention, an output from each of the plurality of second sense circuits and an output from the fourth sense circuit are shorcircuitable, and the output from the fourth sense circuit is output through an inverter circuit.
In one embodiment of the invention, the load circuit of each of the plurality of second sense circuits of the reference voltage generation circuit is a P-channel transistor, and the load circuit of the fourth sense circuit is a P-channel transistor. A gate electrode and a drain electrode of one of the plurality of second sense circuits are connected to a gate electrode of the P-channel transistor of the fourth sense circuit, so that a load characteristic of the fourth sense circuit is equal to a load characteristic of the one of the plurality of second sense circuits.
In one embodiment of the invention, the reference voltage generation circuit shortcircuits an output from the fourth sense circuit and an output from the one of the plurality of second sense circuits through a transistor, and the output from the fourth sense circuit and the output from the one of the plurality of second sense circuits are transferred to a respective prescribed potential from the same level after being released from the shortcircuiting.
In one embodiment of the invention, the memory reading circuit for a semiconductor memory device includes the above-described reference voltage generation circuit; a third sense circuit connected to a selected memory cell and having an N-channel transistor, a P-channel transistor, a plurality of input ends and a plurality of output ends; and a fourth sense circuit for receiving an output from the third sense circuit, the fourth sense circuit having a load circuit, an N-channel transistor, a plurality of input ends and a plurality of output ends. The information is read using an output from each of the plurality of second sense circuits and an output from the fourth sense circuit.
In one embodiment of the invention, in the memory reading circuit for reading information from the selected memory cell by supplying a reference voltage to one of two input ends of a sense amplifier and supplying a voltage from the selected memory cell to the other of the two input ends, an output from each of the plurality of second sense circuits and an output from the fourth sense circuit are input to the sense amplifier.
In one embodiment of the invention, the load circuit of each of the plurality of second sense circuits of the reference voltage generation circuit is a P-channel transistor, and the load circuit of the fourth sense circuit is a P-channel transistor. A gate electrode and a drain electrode of one of the plurality of second sense circuits are connected to a gate electrode of the P-channel transistor of the fourth sense circuit, so that a load characteristic of the fourth sense circuit is equal to a load characteristic of the one of the plurality of second sense circuits.
In one embodiment of the invention, the reference voltage generation circuit shortcircuits an output from the fourth sense circuit and an output from the one of the plurality of second sense circuits through a transistor, and the output from the fourth sense circuit and the output from the one of the plurality of second sense circuits are transferred to a respective prescribed potential from the same level after being released from the shortcircuiting.
In one embodiment of the invention, the memory reading circuit further includes a load circuit for performing current-to-voltage conversion of the selected memory cell and the reference cell, the load circuit including at least one of a transistor and a resistor, wherein the load circuit is directly connected to a drain electrode of the selected memory cell and the drain electrode of the reference cell.
In one embodiment of the invention, an output from each of the plurality of second sense circuits and an output from the fourth sense circuit are shortcircuitable, and the output from the fourth sense circuit is output through an inverter circuit.
In one embodiment of the invention, the load circuit of each of the plurality of second sense circuits of the reference voltage generation circuit is a P-channel transistor, and the load circuit of the fourth sense circuit is a P-channel transistor. A gate electrode and a drain electrode of one of the plurality of second sense circuits are connected to a gate electrode of the P-channel transistor of the fourth sense circuit, so that a load characteristic of the fourth sense circuit is equal to a load characteristic of the one of the plurality of second sense circuits.
In one embodiment of the invention, the reference voltage generation circuit shortcircuits an output from the fourth sense circuit and an output from the one of the plurality of second sense circuits through a transistor, and the output from the fourth sense circuit and the output from the one of the plurality of second sense circuits are transferred to a respective prescribed potential from the same level after being released from the shortcircuiting.
In one embodiment of the invention, the memory reading circuit further includes a load circuit for performing current-to-voltage conversion of the selected memory cell and the reference cell, the load circuit including at least one of a transistor and a resistor, wherein the load circuit is directly connected to a drain electrode of the selected memory cell and the drain electrode of the reference cell.
In one embodiment of the invention, an electronic information device capable of reading information using the above-described memory reading circuit is provided.
According to one aspect of the invention, a reference voltage generation circuit includes at least one reference cell having a source electrode and a drain electrode; a plurality of first pre-sense circuits connected to the reference cell and including an N-channel transistor, a P-channel transistor, a plurality of input ends and a plurality of output ends; and a plurality of second pre-sense circuits each for receiving an output from a corresponding one of the plurality of first pre-sense circuits, the plurality of second pre-sense circuits each having a load circuit, an N-channel transistor, a plurality of input ends and a plurality of output ends.
In one embodiment of the invention, the plurality of first pre-sense circuits each generate a first duplicate voltage based on a voltage from the reference cell, and the plurality of second pre-sense circuits each generate a second duplicate voltage based on the first duplicate voltage.
In one embodiment of the invention, a memory reading circuit for a semiconductor memory device for reading information from a selected memory cell by supplying a reference voltage to one of two input ends of a sense amplifier and supplying a voltage from the selected memory cell to the other of the two input ends is provided. The memory reading circuit includes a reference voltage generation circuit described above; a third pre-sense circuit connected to the selected memory cell and having an N-channel transistor, a P-channel transistor, a plurality of input ends and a plurality of output ends; and a fourth pre-sense circuit for receiving an output from the third pre-sense circuit, the fourth pre-sense circuit having a load circuit, an N-channel transistor, a plurality of input ends and a plurality of output ends. An output from each of the plurality of second pre-sense circuits and an output from the third pre-sense circuit are input to the sense amplifier.
In one embodiment of the invention, the load circuit of each of the plurality of second pre-sense circuits of the reference voltage generation circuit is a P-channel transistor, and the load circuit of the fourth pre-sense circuit is a P-channel transistor. A gate electrode and a drain electrode of one of the plurality of second pre-sense circuits are connected to a gate electrode of the P-channel transistor of the fourth pre-sense circuit, so that a load characteristic of the fourth pre-sense circuit is equal to a load characteristic of the one of the plurality of second pre-sense circuits.
In one embodiment of the invention, the reference voltage generation circuit shortcircuits an output from the fourth pre-sense circuit and an output from the one of the plurality of second pre-sense circuits through a transistor, and the output from the fourth pre-sense circuit and the output from the one of the plurality of second pre-sense circuits are transferred to a respective prescribed potential from the same level after being released from the shortcircuiting.
In one embodiment of the invention, the memory reading circuit further includes a load circuit for performing current-to-voltage conversion of the selected memory cell and the reference cell, the load circuit including at least one of a transistor and a resistor, wherein the load circuit is directly connected to a drain electrode of the selected memory cell and the drain electrode of the reference cell.
In one embodiment of the invention, a memory reading circuit for a semiconductor memory device for reading information from a selected memory cell by supplying a reference voltage to one of two input ends of a sense amplifier and supplying a voltage from the selected memory cell to the other of the two input ends is provided. The memory reading circuit includes a reference voltage generation circuit described above; a third pre-sense circuit connected to the selected memory cell and having an N-channel transistor, a P-channel transistor, a plurality of input ends and a plurality of output ends; and a fourth pre-sense circuit for receiving an output from the third pre-sense circuit, the fourth pre-sense circuit having a load circuit, an N-channel transistor, a plurality of input ends and a plurality of output ends. An output from each of the plurality of second pre-sense circuits and an output from the third pre-sense circuit are input to the sense amplifier.
In one embodiment of the invention, the load circuit of each of the plurality of second pre-sense circuits of the reference voltage generation circuit is a P-channel transistor, and the load circuit of the fourth pre-sense circuit is a P-channel transistor. A gate electrode and a drain electrode of one of the plurality of second pre-sense circuits are connected to a gate electrode of the P-channel transistor of the fourth pre-sense circuit, so that a load characteristic of the fourth pre-sense circuit is equal to a load characteristic of the one of the plurality of second pre-sense circuits.
In one embodiment of the invention, the reference voltage generation circuit shortcircuits an output from the fourth pre-sense circuit and an output from the one of the plurality of second pre-sense circuits through a transistor, and the output from the fourth pre-sense circuit and the output from the one of the plurality of second pre-sense circuits are transferred to a respective prescribed potential from the same level after being released from the shortcircuiting.
In one embodiment of the invention, the memory reading circuit further includes a load circuit for performing current-to-voltage conversion of the selected memory cell and the reference cell, the load circuit including at least one of a transistor and a resistor, wherein the load circuit is directly connected to a drain electrode of the selected memory cell and the drain electrode of the reference cell.
According to another aspect of the invention, an electronic information device capable of reading information uses a memory reading circuit described above.
According to another aspect of the invention, an electronic information device capable of reading information uses a reference voltage generation circuit described above.
Thus, the invention described herein makes possible the advantages of providing a reference voltage generation circuit, used for a semiconductor memory device, for generating a plurality of reference voltages having reduced timewise delay so that when one reference cell is connected to the plurality of comparator circuits, a plurality of comparator circuits are simultaneously operated with reduced influence caused by a coupling effect; a memory reading circuit including such a reference voltage generation circuit; and an electronic information device using such a memory reading circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.